This invention relates to pulse forming circuitry, and in particular to circuitry for generating non-overlapping complementary waveforms.
Frequently in electronic switching operations where a plurality of switches are alternately opened and closed electronically, it is desirable to open particular switches before alternate switches are closed. A particular example is in voltage multiplier circuits i.e. DC-DC converters, (see U.S. Pat. No. 3,955,353 or U.S. Pat. No. 4,106,086). Many circuits of this type require two phase or complementary clock pulse signals where the leading and trailing edges of the pulses of one phase do not overlap the trailing and leading edges of the second phase.
In generating non-overlapping two phase signals it is known to (a) develop complementary pulse signals wherein the leading and trailing edges of the first phase signal are substantially coincident with the trailing and leading edges of the second phase, (b) to add an incremental delay to the leading (trailing) edge of both phase signals i.e. slow the pulse transition in one direction from one state to the other and (c) apply the altered signals to high gain inverters or to threshold detectors with the result of speeding up the slowed transition and changing the duty cycle of the respective waveforms. The duty cycle of the waveform is changed due to the relative point in time at which the inverter responds to the slowed waveform transition--(e.g. the trailing edges) and the normal waveform transition (e.g. the leading edges). The positive portion of each cycle is thus reduced with respect to the relatively negative portion of each cycle of signal for both of the complementary waveforms eliminating the period of first and second phase coincidence or overlap. See for example the article "C-MOS makes voltage converter a paragon of efficiency" by D. Bingham at page 141 of the Sept. 11, 1980 issue of Electronics magazine.